PCI Bus Mastering is always a bit fuzzy.
In the olden days, the “IDE Busmaster” setting used to allow an add-in IDE/ATAPI (PATA, for you younger folks) controller board to control the bus and do direct communication without the CPU/OS.
These days it tends to be something fuzzier.
The danger in allowing bus master is that a high-bandwidth/high-traffic device might “hog” the bus and starve other devices of I/O.
In this case, it might simply have been that allowing bus master keeps the card “on” somehow and doesn’t give the Drobo the “break” it needs to complete its boot.
As a side note, there are three common BIOS settings that have been voodoo-ish (ie, sometimes good, sometime bad, always mysterious):
- PCI Bus Master
- Spread Spectrum Modulation
- PCI Latency Timer
#1 I already described.
#2 is designed to allow the system clocks to be varied to reduce EM emissions.
On some systems I have seen this option actually over- or underclock all the system buses. For devices that are timing-critical (anything that has a clock that’s supposed to somewhat relate to real wall-time - especially prosumer video and audio devices), the clock variances often mess things up because of the changes in timings.
#3 is a fun one. It usually means “the maximum number of attention cycles a device can have before we stop its turn and move to the next device.”
In other words, it’s like setting a time-limit on the how long someone can speak at an event. It’s a limit, not a set slice time - if the speaker (device) is done, it can end early.
A longer time limit means a person could communicate a lot of information, but it also risks that someone else may simply not get their turn.
A shorter time limit means all the speakers get a turn to speak, but they may not be able to communicate their entire message and their message may be fragmented across multiple rounds, or not be delivered in its entirety.
Most times this one defaults to 32 or 64.
If there are high-traffic devices (again, video capture boards fit this) this can sometimes provide a huge throughput benefit by being set to 128 or 192. I’ve seen cases where it needed to be increased to 256, though that is rare.
On the other hand, if there are devices that require constant attention (or have small buffers), the increased latency between attention cycles can cause buffer overflow or loss.